Bus systems of various types have been known for a long time. The master/slave bus systems this invention is based on mostly have the property that all slave must have unique addresses to be addressed individually. Each slave can be addressed individually in this way, wherein settings of the slave can be changed or status information can be queried from the slave. Bus systems of the most varied types, such as master-slave bus systems, have been known for a long time in prior art.
In many master-slave bus systems, the master unit can individually identify and address the slave units of the system. In this way, a master unit is for example capable to operate a system component triggered by a specific slave unit or to assign messages received to a specific slave unit and thus to a specific system component. To provide such functionality, the slave unit on the one hand needs an address that is unique throughout the system; on the other hand, the master unit must know the unique address and the association of the slave unit with a system component or its position in the bus system.
This is conventionally achieved, for example, by performing an addressing or orientation phase during the initialization of a bus system. In this phase, system addresses are assigned to the slave units in a certain order, or the master unit is given the opportunity to query successively stored device identifiers of individual slave units at various positions. For example, addresses are assigned to the slave units manually in that the existing slaves are connected to the bus system individually one after the other or are released for addressing individually one after the other using a manually operated switch. Because only one defined, manually selected slave unit is connected to the bus line or released for addressing, the master unit can assign a unique address to this individual slave unit by outputting a broadcast command on the bus—which is actually directed to all slave units attached to the bus system. Due to the defined order in which the slave units are addressed, the master unit knows the relative position of each slave unit in the system after address allocation. Such manual methods are time consuming and susceptible to errors since they involve a person.
DE 103 36 301 A1 proposes an automated addressing process. A bus-based addressing system of slave units is known from EP 2 287 689 EP. The solutions known from prior art require respective system components for implementing the addressing method and for implementing the bus architecture, all of which causing extra costs and needing installation space. Measures for the subsequent configuration of address allocation are also necessary when replacing a plant component that is connected to a slave, such as a fan.
DE 10 2014 117 797.5 A1 therefore proposes a master-slave system including a master unit having a digital output for providing a signal or a serial signal sequence of signals, and multiple slave units, wherein each of the slave units includes one digital serial memory having a size of one bit, and each slave unit includes an input and an output, wherein the slave units are serially connected to one another via the inputs and the outputs via a signal line, and wherein the input of a first slave unit is connected via the signal line to the digital output of the master unit. The master-slave system is configured such that a signal (signal change) of a serial signal sequence supplied by the digital output is detected at the input of the slave unit, in order to raise the address of the corresponding slave unit in each case by the value “1”, to store the signal change in the memory and to output a signal corresponding to the content of the memory at the output of the memory.
It is a disadvantage of this addressing method that addressing via shift registers requires a clock signal from the master and addressing does not run quasi-automatically after the system start.
U.S. Pat. No. 8,856,413 B2 discloses a dynamically addressable slave unit including an interface bus, an enable circuit having a switch and two control ports which are connected via the enable circuit. The system is configured such that address allocation is only possible if the bus interface control signal is present at one of the ports and the signal switch is open to control the release. Otherwise the enable circuit locks the slave unit. The disadvantage of this method is that a special circuit is required to perform the addressing.
There is also a need for performing the addressing in an ascending address order and to eliminate errors automatically during address transfer (that is, without manual intervention).